1. Field of the Invention
This invention generally relates to an incrementer circuit for use in a semiconductor device, and, in particular, to an incrementer circuit, for example, for use in a microprogram controller.
2. Description of the Prior Art
A microprogram controller for use in a microcomputer or the like is disclosed in Japanese Patent Laid-open Publication No. 62-216229. The microprogram controller disclosed in this publication includes an incrementer circuit which outputs an input address data by adding 1 thereto if a Hi level carry in signal is input; whereas, the address data is output without alteration if a Hi level carry in signal is not input.
FIG. 2 schematically illustrates a typical prior art incrementer circuit for processing an 8-bit address data. In FIG. 2, the respective bits b1 through b8 of an 8-bit address data are supplied to respective second input terminals of exclusive NOR gates XNOR1 through XNOR8 via respective data input terminals DI1 through DI8. The respective bits b1 through b7 of the address data input to the data input terminals DI1 through DI7 are also input into respective first input terminals of NOR gates NOR1 through NOR7 via respective inverters INV11 through INV17. A carry in signal is applied in the form of a carry signal C0 to the second input terminal of the NOR gate NOR1 and also to the first input terminal of the exclusive NOR gate XNOR1 via an input terminal CI and an inverter INV1.
If a Hi level carry in signal has been input and the bit b1 is at Hi level, then the NOR gate NOR1 outputs a Hi level carry signal C1 to the second input terminal of the NOR gate NOR2 and also to the first input terminal of the exclusive NOR gate XNOR2 via an inverter INV2. If the carry signal C1 is at Hi level and the bit b2 is also at Hi level, then the NOR gate NOR2 outputs a Hi level carry signal C2 to the second input terminal of the NOR gate NOR3 and also to the first input terminal of the exclusive NOR gate XNOR3 via an inverter INV3. Similarly, if each of carry signals C2 through C5 is at Hi level and the corresponding one of the bits b3 through b6 is at Hi level, then each of the NOR gates NOR3 through NOR6 outputs a corresponding one of Hi level carry signals C3 through C6 to the second input terminal of a corresponding one of the NOR gates NOR4 through NOR7 and also to the first input terminal of a corresponding one of the exclusive NOR gates XNOR4 through XNOR7 via a corresponding one of inverters INV4 through INV7. In addition, if the carry signal C6 is at Hi level and the bit b7 is at Hi level, then the NOR gate NOR7 outputs a Hi level carry signal C7 to the first input terminal of the exclusive NOR gate XNOR8 via an inverter INV8.
As a result, if a Hi level carry in signal is input, the exclusive NOR gates XNOR1 through XNOR8 increment the address data input into the data input terminals DI1 through DI8 by "1", respectively, and output its result to the data output terminals DO1 through DO8. Thus, with the incrementer circuit having the above-described structure, when a Hi level carry in signal has been input into the input terminal CI, an 8-bit address data b1 through b8 input into the data input terminals DI1 through DI8 is incremented by "1" and output to the data output terminals DO1 through DO8. On the other hand, if a Lo level carry in signal has been input into the input terminal CI, an 8-bit address data b1 through b8 input into the data input terminals DI1 through DI8 is output to the data output terminals DO1 through DO8 without alteration.
In an incrementer circuit as described above, carry signals C1 through C7 are sequentially generated by the NOR gates NOR1 through NOR7 one after another so that it takes a relatively long period of time from the time when an address data has been input to the time when the most significant bit carry signal C7 is produced to obtain an incremented address data.